In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.
A sub-circuit SPICE model of a MOSFET for low temperature operation is presented.Two resistors are introduced for the freeze-out effect,and the explicit behavioral models are developed for them.The model can be used in a wide temperature range covering both cryogenic temperature and regular temperatures.
The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance.
A measuring technique based on the CP（charge pumping）method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth.The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail.At the same time,the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed.The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.
