With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET,including the new mechanisms to induced SEUs,the advances of the MCUs and some newly observed phenomena of the SETs.The mechanisms and the trends with downscaling of these issues are briefly discussed.We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing,modeling and hardening assurance of soft error issues we have to address in the future.
In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.
