Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.
A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.
A two-probe system was established for a finite (7, 0) silicon carbide (SiC) nanotube coupled to Au (111) surfaces via Au-C bonds. Using the non-equilibrium Green function (NEGF) combined with density functional theory (DFT), the above system was studied for its electronic transport properties. Negative differential resistance (NDR) was observed when the bias voltage was greater than 1.4 V. Because the transport properties of the system were sensitive to the applied bias voltage, NDR might be caused by the fluctuation of the transmission coefficient with the bias voltage.
YANG YinTang SONG diuXu LIU HongXia CHAI ChangChun
