A fully integrated soft-start circuit for DC-DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections： an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 um CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 us start-up time. The inductor current and the output voltage increase smoothly over the whole load range.
A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF （power factor） with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The 0.02 s without overshoot. The experimental results startup and the recovery times respectively are about 0.1 s and also verify the validity of the proposed method.
The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.
