This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.
This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system.It is based on up-conversion with a high linearity passive mixer.Unlike the traditional BPSK modulation scheme,the local oscillator （LO） is modulated by the baseband data instead of the pulse.The chip is designed and fabricated by standard 0.18μm CMOS technology.The transmitter achieves a high data rate up to 400 Mbps.The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier.The maximum peak-to-peak amplitude of the pulse is 600 mV.It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate.The energy efficiency is 91.4 pJ/pulse.The die area is 1.4×1.4 mm^2.
A low power high gain differential UWB low noise amplifier （LNA） operating at 3-5 GHz is presented. A common gate input stage is used for wideband input matching; capacitor cross coupling （CCC） and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure （NF） of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4,4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption （3 mA from a 1.5 V supply）. The proposed differential LNA occupies an area of 1,01 mm^2 including test pads.
A differential power amplifier （PA）, designed using the linear-phase filter model, for a BPSK modulated ultra-wideband （UWB） system operating in the 3-5 GHz frequency range is presented. The proposed PA was fabricated using 0.18μm SMIC CMOS technology. To achieve sufficient linearity and efficiency, this PA operates in the class-AB region, delivering an output power of 8.5 dBm at an input-1 dB compression point of-0.5 dBm. It consumes 28.8 mW, realizing a fiat gain of 9.11± 0.39 dB and a very low group delay ripple of ±8 ps across the whole band of operation.
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.
