A two-step exposure method to effectively reduce the proximity effect in fabricating nanometer-spaced nanopillars is presented. In this method, nanopillar patterns on poly-methylmethacrylate （PMMA） were partly crosslinked in the first-step exposure. After development, PMMA between nanopillar patterns was removed, and hence the proximity effect would not take place there in the subsequent exposure. In the second-step exposure, PMMA masks were completely cross-linked to achieve good resistance in inductively coupled plasma etching. Accurate pattern transfer of rows of nanopillars with spacing down to 40 nm was realized on a silicon-on-insulator substrate.
Comparisons are performed to study the drive current of accumulation-mode（AM） p-channel wrap-gated Fin-FETs.The drive current of the AM p-channel FET is 15%-26%larger than that of the inversion-mode （IM） p-channel FET with the same wrap-gated fin channel,because of the body current component in the AM FET, which becomes less dominative as the gate overdrive becomes larger.The drive currents of the AM p-channel wrap-gated Fin-FETs are 50%larger than those of the AM p-channel planar FETs,which arises from effective conducting surface broadening and volume accumulation in the AM wrap-gated Fin-FETs.The effective conducting surface broadening is due to wrap-gate-induced multi-surface conduction,while the volume accumulation,namely the majority carrier concentration anywhere in the fin cross section exceeding the fin doping density,is due to the coupling of electric fields from different parts of the wrap gate.Moreover,for AM p-channel wrap-gated Fin-FETs, the current in channel along 110 is larger than that in channel along 100,which arises from the surface mobility difference due to different transport directions and surface orientations.That is more obvious as the gate overdrive becomes larger,when the surface current component plays a more dominative role in the total current.
Silicon crystal-facet-dependent nanostructures have been successfully fabricated on a （100）-oriented silicon-oninsulator wafer using electron-beam lithography and the silicon anisotropic wet etching technique. This technique takes advantage of the large difference in etching properties for different crystallographic planes in alkaline solution. The minimum size of the trapezoidal top for those Si nanostructures can be reduced to less than 10nm. Scanning electron microscopy （SEM） and atomic force microscopy （AFM） observations indicate that the etched nanostructures have controllable shapes and smooth surfaces.
A novel simple dose-compensation method is developed for proximity effect correction in electron-beam lithography.The sizes of exposed patterns depend on dose factors while other exposure parameters（including accelerate voltage,resist thickness,exposing step size,substrate material,and so on） remain constant.This method is based on two reasonable assumptions in the evaluation of the compensated dose factor：one is that the relation between dose factors and circle-diameters is linear in the range under consideration;the other is that the compensated dose factor is only affected by the nearest neighbors for simplicity.Four-layer-hexagon photonic crystal structures were fabricated as test patterns to demonstrate this method.Compared to the uncorrected structures,the homogeneity of the corrected hole-size in photonic crystal structures was clearly improved.
