This paper presents an algorithm that can adaptively select the intermediate frequency（IF） and compensate the IQ mismatch according to the power ratio of the adjacent channel interference to the desired signal in a low-IF GSM receiver.The IF can be adaptively selected between 100 and 130 kHz.Test result shows an improvement of phase error from 6.78°to 3.23°.Also a least mean squares（LMS） based IQ mismatch compensation algorithm is applied to improve image rejection ratio（IRR） for the desired signal along with strong adjacent channel interference.The IRR is improved from 29.1 to 44.3 dB in measurement.The design is verified in a low-IF GSM receiver fabricated in SMIC 0.13μm RF CMOS process with a working voltage of 1.2 V.
A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.
This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm;and 0.48×0.25 mm;areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）;according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.
