Three linear CMOS power amplifiers(PAs) with high output power(more than watt-level output power)for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer(PCT) and one 1.95 GHz PA using an on-chip series combining transformer(SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors(MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC0.18 m RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 d B and 34.3 d B, a maximum output power of 30.7 d Bm and 29.4 d Bm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of37.5 d B, a maximum output power of 34.3 d Bm with 36.3% of peak PAE.
随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线性度的方法,并以一款分段式10 bit DAC为例,分别采用简码和传统的全码方法验证了它的微分非线性DNL与积分非线性INL。结果表明,简码测试和全码测试得到的DNL与INL曲线趋势一致,但简码测试效率高,仅占全码测试周期的1/8;另外简码测试减小了负载电阻温漂引入的误差,因此相比全码测试线性度的性能提高了0.1-0.2 LSB。
