This paper presents an ultra-low power incremental ADC for biosensor interface circuits. The ADC consists of a resettable second-order delta-sigma （△ ∑） modulator core and a resettable decimation filter. Several techniques are adopted to minimize its power consumption. A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators. A correlated-double-sampling （CDS） technique is applied to reject the offset and 1/f noise, thereby removing the integrator leakage and relaxing the gain requirement of the OTA. A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply. The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators. The capacitors used in this design are of customized metal-oxide metal （MOM） type to reach the minimum capacitance set by the k T~ C noise limit. Fabricated with a 1P6M 0.18/zm CMOS technology, the presented incremental ADC consumes 600 nW at 2 kS/s from a 1.2 V supply, and achieves 68.3 dB signal to noise and distortion ratio （SNDR） at the Nyquist frequency and an FOM of 0.14 pJ/conversion step. The core area is 100 × 120 μm^2.
This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.
