An integrated phase change memory cell with dual trench epitaxial diode is successfully integrated in the traditional 0.13μm CMOS technology.By using dual trench isolated structure in the memory cell,it is feasible to employ a Si-diode as a selector for integration in a crossbar structure for high-density phase change memory even at 45 nm technology node and beyond.A cross-point memory selector with a large on/off current ratio is demonstrated,the diode provides nine orders of magnitude isolation between forward and reverse biases in the SET state.A low SET programming current of 0.7mA is achieved and RESET/SET resistance difference of 10000×is obtained.
Ge2Sb2Te5 gap filling is one of the key processes for phase-change random access memory manufacture. Physical vapor deposition is the mainstream method of Ge2Sb2Te5 film deposition due to its advantages of film quality, purity, and accurate composition control. However,the conventional physical vapor deposition process cannot meet the gap- filling requirement with the critical device dimension scaling down to 90 nm or below. In this study, we find that the deposit-etch-deposit process shows better gap-filling capability and scalability than the single-step deposition process, especially at the nano-scale critical dimension. The gap-filling mechanism of the deposit-etch-deposit process was briefly discussed. We also find that re-deposition of phase-change material from via the sidewall to via the bottom by argon ion bombardment during the etch step was a key ingredient for the final good gap filling. We achieve void-free gap filling of phase-change material on the 45-nm via the two-cycle deposit-etch-deposit process. We gain a rather comprehensive insight into the mechanism of deposit-etch-deposit process and propose a potential gap-filling solution for over 45-nm technology nodes for phase-change random access memory.
Phase change random access memory （PCRAM） is one of the best candidates for next generation non- volatile memory, and phase change SiESbETe5 material is expected to be a promising material for PCRAM. In the fabrication of phase change random access memories, the etching process is a critical step. In this paper, the etching characteristics of Si2Sb2Te5 films were studied with a CF4/Ar gas mixture using a reactive ion etching system. We observed a monotonic decrease in etch rate with decreasing CF4 concentration, meanwhile, Ar concentration went up and smoother etched surfaces were obtained. It proves that CF4 determines the etch rate while Ar plays an im- portant role in defining the smoothness of the etched surface and sidewall edge acuity. Compared with GeESbETe5, it is found that Si2Sb2Te5 has a greater etch rate. Etching characteristics of Si2SbETe5 as a function of power and pressure were also studied. The smoothest surfaces and most vertical sidewalls were achieved using a CF4/Ar gas mixture ratio of 10/40, a background pressure of 40 mTorr, and power of 200 W.
The dry etching characteristic of AlSbTe film was investigated by using a CF/Ar gas mixture.The experimental control parameters were gas flow rate into the chamber,CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power applied to the lower electrode.The total flow rate was 50 sccm and the behavior of etch rate of AlSbTe thin films was investigated as a function of the CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power.Then the parameters were optimized.The fast etch rate was up to 70.8 nm/min and a smooth surface was achieved using optimized etching parameters of CFconcentration of 4%,power of 300 W and pressure of 80 mTorr.
A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
The results of adhesion improvement and SET-RESET operation voltage reduction for the GeN buffer layer are presented.It is found that the adhesive strength between the Ge_(2)Sb_(2)Te_(5)(GST)layer and the layer below could be increased at least 20 times,which is beneficial for solving the phase change material peeling issue in the fabrication process of phase change memory(PCM).Meanwhile,the RESET voltage of the PCM cell with a 3-nm-thick GeN buffer layer can be reduced from 3.5 V to 2.2 V.The GeN buffer layer will play an important role in high density and low power consumption PCM applications.
Sb rich Ge_(2)Sb_(5)Te_(5) materials are investigated for use as the storage medium for high-speed phase change memory(PCM).Compared with conventional Ge2Sb2Te5,Ge_(2)Sb_(5)Te_(5) films have a higher crystallisation temperature(~200℃),larger crystallisation activation energy(3.13 eV),and a better data retention ability(100.2℃ for ten years).A reversible switching between set and reset states can be realised by an electric pulse as short as 5 ns for Ge_(2)Sb_(5)Te_(5)-based PCM cells,over 10 times faster than the Ge_(2)Sb_(5)Te_(5)-based one.In addition,Ge2Sb2Te5 shows a good endurance up to 3×10^(6) cycles with a resistance ratio of about three orders of magnitude.This work clearly reveals the highly promising potential of Ge_(2)Sb_(5)Te_(5) films for applications in high-speed PCM.
Phase-change line memory cells with different line widths are fabricated using focused-ion-beam deposited C-Pt as a hard mask. The electrical performance of these memory devices was characterized. The current^oltage （I-V） and resistance-voltage （RV） characteristics demonstrate that the power consumption decreases with the width of the phase-change line. A three-dimensional simulation is carried out to further study the scaling properties of the phase- change line memory. The results show that the resistive amorphous （RESET） power consumption is proportional to the cross-sectional area of the phase-change line, but increases as the line length decreases.
Along with a series of research works on the physical prototype and properties of the memory cell,an SPICE model for phase-change memory（PCM） simulations based on Verilog-A language is presented.By handling it with the heat distribution algorithm,threshold switching theory and the crystallization kinetic model,the proposed SPICE model can effectively reproduce the physical behaviors of the phase-change memory cell.In particular,it can emulate the cell＇s temperature curve and crystallinity profile during the programming process,which can enable us to clearly understand the PCM＇s working principle and program process.
