A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9"segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT(process, source voltage and temperature) corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31"decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer(DDS) chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm^2 including bond pads(DAC only), and the measured performance is SFDR > 40 d B(with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized),this paper DAC's clock frequency(2.5 GHz) and higher output frequency SFDR(> 40 d B, up to 1 GHz) has some competition.
In this paper, the effect of floating body effect(FBE) on a single event transient generation mechanism in fully depleted(FD) silicon-on-insulator(SOI) technology is investigated using three-dimensional technology computer-aided design(3DTCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect(FBE) whether for positive or negative channel metal oxide semiconductor(PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking(IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.
Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor(Fin FET)technology. However, the studies of charge sharing induced single-event transient(SET) pulse quenching with bulk Fin FET are reported seldomly. Using three-dimensional technology computer aided design(3DTCAD) mixed-mode simulations,the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk Fin FET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing(RBB), the circuit with forward body-biasing(FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least.This can provide guidance for radiation-hardened bulk Fin FET technology especially in low power and high performance applications.
