A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.
XU Zhi-gangCHEN Ying-meiWANG TaoCHEN Xue-huiZHANG Li
A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.
Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial （SerDes） clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery （CDR） model show that the jitter specifications exceed the mask of ITU-T optical transport network （OTN） G.8251 recommendations. The whole systems are validated by 9.95-11.5 Gbit/s CDR and the jitter attenuation phase locked loops （PLL） circuits using TSMC 65 nm CMOS technology.
A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.
This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier （LNA）, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier （VGA） and programmable gain amplifier （PGA） provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads.
CHEN Ying-mei LI Zhi-qun WANG Zhi-gong JING Yong-kang ZHANG Li
A design of 13 Gbit/s vertical cavity surface emitting laser （VCSEL） driver using 0.18 μm complementary metal oxide semiconductor （CMOS） technology is presented in this paper. The core unit of the driver consists of pre-amplify stage and output stage circuit. Techniques of three stages differential amplifier with low impedance load and active feedback are employed in pre-amplify stage, and technique of C3A is adopted in output stage to acquire low power consumption and high speed. The experimental results show that the circuit can work at the data rate of 10 Gbit/s and maximum of 13.2 Gbit/s. The output modulation current is up to 12.5 mA and the power dissipation is only 68 mW with a 1.8 V power supply.
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
A novel 10 GHz eight-phase voltage-controlled oscillator （VCO） architecture applied in clock and data recovery （CDR） circuit for 40 Gbit/s optical communications system is proposed. Compared with the traditional eight-phase oscillator, a new ring CL ladder filter structure with four inductors is proposed. The VCO is designed and fabricated in IBM 90 nm complementary metal-oxide-semiconductor transistor （CMOS） technology. Measurement results show the tuning range is 9.2 GHz-11.0 GHz and the phase noise of - 108.85 dBc/Hz at 1 MHz offset from the carrier frequency of 10 GHz. The chip area of VCO is 500 μm × 685 μm and the power dissipation is 17.4 mW with the 1.2 V supply voltage.
