This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.
An active-RC low-pass filter of 5MHz cutoff frequency with a tuning architecture is proposed. It is implemented in 0. 18μm standard CMOS technology. The accuracy of the tuning system is improved to be within （ - 1.24%, ＋ 2.16%） in measurement. The chip area of the tuning system is only a quarter of that of the main-filter. After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The in-band 3rd order harmonic input intercept point （IIP3） is larger than 16. ldBm, with 50Ω as the source impedance. The input referred noise is about 36μVrms The measured group delay variation of the filter between 3 and 5MHz is only 24ns,and the filter power consump- tion is 3.6roW. This filter with the tuning system is realized easily and can be used in many wireless low-IF receiver applications, such as global position systems （GPS）, global system for mobile communications （GSM） and code division multiple access （CDMA） chips.
