Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.
Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.
A 0. 1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated. The groove depth is 180nm. The transfer characteristics and the output characteristics are shown. At Vds = -1. 5V,the drain saturation current is 380μA and the off-state leakage current is 1.9nA;the sub-threshold slope is 115mV/dec at Vds = -0. 1V and DIBL factor is 70. 7mV/V. The electrical characteristic comparison between the 0.1μm SOI groovedgate pMOSFET and the 0. 1μm bulk grooved gate one with the same process demonstrates that a 0. 1μm SOI grooved gate pMOSFET has better characteristics in current-driving capability and sub-threshold slope.
FB （floating-body） and BC （body-contact） partially depleted SOI nMOSFETs with HBC（half-back-channel） implantation are fabricated. Test results show that such devices have good performance in delaying the occurrence of the “kink” phenomenon and improving the breakdown voltage as compared to conventional PDSOI nMOS- FETs,while not decreasing the threshold voltage of the back gate obviously. Numerical simulation shows that a reduced electrical field in the drain contributes to the improvement of the breakdown voltage and a delay of the “kink” effect. A detailed analysis is given for the cause of such improvement of breakdown voltage and the delay of the “kink” effect.
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
